Integrated circuit devices typically transmit and receive information synchronous with clock signals. Typically, transitions of a clock signal indicate that valid information is available on a signal line or set of signal lines coupled to the integrated circuit device. The clock signals that synchronize information transfer must satisfy input and output timing parameters for the integrated circuit device.
The integrated circuit device typically has a specified input setup time (t.sub.SU) and input hold time (t.sub.H). Input data must be present and stable on the device input pins from at least t.sub.SU before the clock transition and until at least t.sub.H after clock transition for proper operation. Also, the integrated circuit device typically has a specified minimum propagation time from clock to output (t.sub.CLK-Q). Output data is not valid on the output pins of the device until at least t.sub.CLK-Q after the clock transition.
The input and output timing parameters of an integrated circuit device typically must be tested to ensure proper operation of the device in a high speed system. Limitations in the measurement capability of test equipment, however, can in some cases cause inaccuracies in timing measurements. The inaccuracies typically can create a band of uncertainty for the input and output timing parameters of a device. Devices having measured timing parameters within the band of uncertainty are typically rejected, even though the devices would meet the required timing parameters if the test equipment were more accurate.
For example, test equipment having an overall timing accuracy of 800 picoseconds (ps) is typically sufficient to measure devices for a system having a cycle time of 50 nanoseconds (ns). Unfortunately, such test equipment performance is insufficient for devices having a 2 ns cycle time. An overall timing accuracy of 800 ps creates measurement inaccuracies equivalent to 40% of the 2 ns cycle time. The high level of inaccuracy results in a high rate of improper rejection of devices.